This invention relates generally to automatic gain control circuitry, and more particularly the invention is directed to automatic gain control for signals with diverse power level ranges such as signals sent by wireless transmission.
Broadcast signals such as cellular telephone signals are received by antenna means and converted to digital form by an analog digital converter (ADC) for demodulation and processing. Due to the varying power level of wireless transmitted signals, an automatic gain control circuit (AGC) is normally included before the ADC for proper conversion of the analog signals. For example, the low power Bluetooth standard for wireless transmitted signals provides a 4 pulse preamble for AGC and DC offset calibration before transmitted data. This necessitates an AGC circuit which has fast response in signal acquisition and gain control.
Heretofore, feedback control to the AGC has been implemented in two architectures, one purely analog and another mixed-signal i.e., analog and digital. The analog feedback control architecture uses an analog RSSI to determine signal voltage/power and feeds back an analog control voltage. This requires the AGC control to be analog, which means that no digital intelligence can be implemented within the loop. The result is normally a slow response to large signal power discontinuities or AGC loop ringing due to loop overshoot.
The mixed-signal prior art architecture feedback to the AGC has been taken after the ADC circuit which necessitates a digital to analog conversion for the feedback control signal. Further, a Receive Signal Strength Indicator (RSSI) circuit has been provided in the CPU and logic block which receives the digital signals from the ADC circuit. The RSSI circuit can provide an indication of voltage or power range of the signal and provide feedback to the AGC circuitry. However, this circuitry does not have the response time needed for optimum usage with signals such as Bluetooth.
The present invention is directed to AGC circuitry with enhanced speed of operation in signal acquisition mode.
In accordance with the invention, an analog RSSI circuit is provided in a feedback loop prior to the ADC circuitry to enhance acquisition speed. The loop combines programmable decision logic to establish a desired voltage level or sweet spot, and a plurality of voltage ranges for fast acquisition and for tracking.
In a preferred embodiment, the AGC architecture includes cascaded variable gain amplifiers (VGA) each with a dynamic gain range equal to the summation of the cascaded VGA gains. The VGA""s are controlled by a digital control circuit, which determines the signal level at the output of the AGC and corrects it to keep the AGC output within the ADC nominal input range.
An analog Receive Signal Strength Indicator (RSSI) and a set of comparators determine the AGC output signal level with respect to predetermined DC threshold settings. This level determination differs from conventional AGC architectures, where the AGC output signal level determination is normally determined in the baseband device. The loop latency of the normal architecture (due to signal power averaging functions) is such that it limits the AGC response time. This in-turn means this architecture cannot react readily to bursty data in the receive channel.
The AGC architecture in accordance with a preferred embodiment of the invention uses comparators to determine when the RSSI signal level is very low, low, high or very high. This in-turn signifies if the AGC output level is very low, low, high or very high. The digital control circuit then increases the VGA gains relative to the measured signal level with very high, high, low, very low gain jumps, so as to bring the AGC output level within the ADC nominal range (sweet spot) within one decision cycle. This is termed a fast attack AGC response. After the fast attack response, the AGC tracks any signal level variations at the input using a tracking mode, where the AGC steps in signal discrete gain increments/decrements. If the AGC input signal should then exceed the very low or very high levels, the fast attack response is entered again.
The boundaries of the very low, low, high and very high ranges are determined by the comparators, and more specifically by the DC reference voltages on the comparator inputs. By altering these DC voltages the range boundaries can be moved relative to each other. The voltage levels are generated using simple Digital-to-Analog Converter (DAC) methods, which allows the DC comparator reference voltages to be digitally controlled. This operation allows the range boundaries to be optimized for the quickest AGC response time and also to allow for compensation for any receive path gain variations from nominal. The digital control circuit gain jumps are also programmable to optimize AGC response time and allow for receive path variation.
The invention and objects and feature thereof will be more readily apparent from the following detailed description and dependent claims when taken with the drawing.